xPU Accelerator Offload Functions
As covered in our
first xPU webcast “SmartNICs
and xPUs: Why is the Use of Accelerators Accelerating,” we discussed the trend to deploy dedicated accelerator chips to
assist or offload the main CPU. These new accelerators (xPUs) have multiple
names such as SmartNIC, DPU, IPU, APU, NAPU. If you missed the presentation, I
encourage you to check it out in the SNIA
Educational Library where you can watch it on-demand and
access the presentation slides.
This second webcast
in this SNIA
Networking Storage Forum xPU webcast series is “xPU
Accelerator Offload Functions” where our SNIA experts will take a deeper
dive into the accelerator offload functions of the xPU. We’ll discuss what
problems the xPUs are coming to solve, where in the system they live, and the functions
they implement, focusing on: Read More